A Survey on Application Specific Processor Architectures for Digital Hearing Aids

On the one hand, processors for hearing aids are highly specialized for audio processing, on the other hand they have to meet challenging hardware restrictions. This paper aims to provide an overview of the requirements, architectures, and implementations of these processors. Special attention is given to the increasingly common application-specific instruction-set processors (ASIPs). The main focus of this paper lies on hardware-related aspects such as the processor architecture, the interfaces, the application specific integrated circuit (ASIC) technology, and the operating conditions. The different hearing aid implementations are compared in terms of power consumption, silicon area, and computing performance for the algorithms used. Challenges for the design of future hearing aid processors are discussed based on current trends and developments

KAVUAKA : Chip Design für digitale Hörhilfen

Am Institut für Mikroelektronische Systeme (IMS) wird im Rahmen des Exzellenzclusters Hearing4all erforscht, wie Signalverarbeitung-Chips für digitale Hörgerätesystemen anhand von komplexen Hörgerätealgorithmen konzipiert und optimiert werden können. Ziel der Forschung ist es, neuartige Prozessorarchitekturen zu entwickeln, die die geforderte hohe Rechenleistung bereitstellen, gleichzeitig einen sehr geringen Stromverbrauch aufweisen und in kleine Hörgerätegehäuse integriert werden können

An Integrated Heated Testbench for Characterizing High Temperature ICs

This paper presents a newly developed integrated heating system, which can keep the IC under test at a constant temperature of up to 250 ◦C. The heating system can be used while the IC under test is mounted on its custom-designed interface board, which controls the two supply voltages and provides connectivity to an FPGA. Using a testing framework on the FPGA, the test stimuli and operating clock can be provided with at least 100 MHz. Thus, it is possible to fully vary all three parameters—frequency, voltage, and temperature—during continuous operation of the IC. A case study is performed with a previously fabricated ASIC to test the proposed system

SmartHeaP – Smart Hearing Aid Processor : Ein industrielles Translationsprojekt für digitale Hörhilfen

Im Smart Hearing Aid Processor Projekt (SmartHeaP) werden die aus dem Exzellenzcluster Hearing4all gewonnenen Erkenntnisse im Bereich der Architektur und Algorithmenentwicklung für digitale Hörgeräte in die Industrie übertragen. Dazu hat sich aus Forschung und Industrie ein großer Projektverbund zusammengeschlossen, um mit Hilfe von modernen Technologien und kommerziellen Softwareframeworks ein neues Hörgerätesystem zu entwickeln. Das System on Chip (SoC) verbindet alle Komponenten, um die gesamte Technologie eines Hörgerätes auf einem Chip zu realisieren

Proceedings of the Linux Audio Conference 2018

These proceedings contain all papers presented at the Linux Audio Conference 2018. The conference took place at c-base, Berlin, from June 7th - 10th, 2018 and was organized in cooperation with the Electronic Music Studio at TU Berlin

COTS – Harsh Condition Effects Considerations from Technology to User Level

Radiation hardened devices are mostly extremely expensive. The continuously downscaling of microelectronic structures and the unavoidable presence of particle radiation on ground and in space leads to unwanted failures in electronic devices. Furthermore it is expected that in the next few years around 8000 new satellites will be launched around the world. Due to the enormous increasing need for Rad-Hard devices, there will be more focus on Commercial Of The Shelf (COTS) devices, which costs are lower. Also nowadays microelectronics for automotive systems are tested to withstand radiation especially SEU-single event upsets. It is clear that SEU cannot be ignored anymore especially in the application of unmanned autonomous vehicles and systems. Reliability testing is expensive and extremely time consuming. The use of COTS-Commercials of the shelf is the ultimate goal to reach. In this paper, an overview of radiation effects on different CMOS technologies used in COTS devices is given. These effects can be considered while selecting different functional equivalent COTS devices implemented with different technologies. Moreover, an overview of software techniques used in programmable commercial devices to reduce the radiation effects is also described

A 4 μ W Low-Power Audio Processor System for Real-Time Jaw Movements Recognition in Grazing Cattle

Precision livestock farming consists of technological tools and techniques to improve livestock management. Proper detection and classification of jaw movement (JM) events are indispensable for the estimation of dry matter intake, detection of health problems, and flag the onset of estrus, among other information. The analysis of acoustic signals is one of the most accepted ways to monitor the feeding behavior of free-grazing cattle. Different acoustic methods have been developed for recognizing JM-events in recent years. However, their operation is limited to off-line analysis on a personal computer. The lack of on-line acoustic monitoring systems is associated with the challenging operation requirements (low-power consumption, autonomy, portability, robustness and non-intrusive on the animal). In this paper, a fixed-point variant of the chew-bite energy-based algorithm is presented. This algorithm is implemented on a new low-power audio processor system for real-time recognition of JM-events. The system includes a Nanocontroller processor, which is always-on and detects JM-events; and a second transport-triggered architecture (TTA) based processor, which is mainly in power-down and classifies JM-events. The results demonstrate that the proposed fixed-point JM-events recognizer achieves a recognition rate of 91.4% and 90.2% in noiseless and noisy conditions, respectively. The recognition rate increases by 6.1% regarding a previous reference on-line system. Moreover, the proposed audio processor system chip consumes 4 μW on average, i.e., only 2.3% of the power of an always-on TTA-based processor system for the same audio sequence. An exemplary implementation of the proposed system in a 65 nm low-leakage CMOS technology is given.Fil: Martínez Rau, Luciano Sebastián. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Santa Fe. Instituto de Investigación en Señales, Sistemas e Inteligencia Computacional. Universidad Nacional del Litoral. Facultad de Ingeniería y Ciencias Hídricas. Instituto de Investigación en Señales, Sistemas e Inteligencia Computacional; ArgentinaFil: Weißbrich, Moritz. Technische Universitat Carolo Wilhelmina Zu Braunschweig.; AlemaniaFil: Payá Vayá, Guillermo. Technische Universitat Carolo Wilhelmina Zu Braunschweig.; Alemani

Vehicle Hardware-In-the-Loop System for ADAS Virtual Testing

International audienc

Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments

Microcontrollers to be used in harsh environmental conditions, e.g., at high temperatures or radiation exposition, need to be fabricated in robust technology nodes in order to operate reliably. However, these nodes are considerably larger than cutting-edge semiconductor technologies and provide less speed, drastically reducing system performance. In order to achieve low silicon area costs, low power consumption and reasonable performance, the processor architecture organization itself is a major influential design point. Parameters like data path width, instruction execution paradigm, code density, memory requirements, advanced control flow mechanisms etc., may have large effects on the design constraints. Application characteristics, like exploitable data parallelism and required arithmetic operations, have to be considered in order to use the implemented processor resources efficiently. In this paper, a design space exploration of five different architectures with MIPS- or ARM-compatible instruction set architectures, as well as transport-triggered instruction execution is presented. Using a 0.18 μ m SOI CMOS technology for high temperature and an exemplary case study from the fields of communication, i.e., powerline communication encoder, the influence of architectural parameters on performance and hardware efficiency is compared. For this application, a transport-triggered architecture configuration has an 8.5× higher performance and 2.4× higher computational energy efficiency at a 1.6× larger total silicon area than an off-the-shelf ARM Cortex-M0 embedded processor, showing the considerable range of design trade-offs for different architectures.publishedVersionPeer reviewe